Figure 5 | Scientific Reports

Figure 5

From: Material to system-level benchmarking of CMOS-integrated RRAM with ultra-fast switching for low power on-chip learning

Figure 5

(a) Diagram showing the complete workflow from device fabrication, to analog switching experiments, to optimal switching condition selection, to device model fitting, hyperparameter optimization, and finally to analog fully in-memory training. (b) Example of hardware data and fitted model for device aware-training. (c) Example of hyperparameter optimization. Here the goal is to extract parameter values that yield the highest accuracy without over or under-fitting. (d) Accuracy plots for both TaOx and HfOx based analog switching conditions. TaOx based device switching (500 µA + 1.4 V −1.3 V) showing close to floating point baseline accuracy.

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