Figure 2
Demonstration of the VCBM and developed factorization machine. (a), Architecture of the D-Wave 2000Q quantum annealer8. The locally connected hardware has limitations for solving complex COPs. (b, c, d), Architectures of graph-model-based factorization machines. Circles represent p-bits, and squares represent the approximate hardware area of the digital logic. (b) The hardware cost of the general Boltzmann machine can be reduced by replacing the 3-body and 4-body terms with hidden p-bits9. However, hidden p-bits also increase hardware complexity. (c) In the graph model, p-bits of the general Boltzmann machine require a large area of spin-weight matrix multiplication logic10. (d) The architecture of the proposed VCBM. The digital input of p-bits can be calculated using the term E(sk = 0) – E(sk = 1). Thus, the energy calculator generates p-bit inputs without spin-weight matrix multiplication. (e), Architecture of our probabilistic factorization machine. In this work, we implemented a prototype of a 64-bit general-purpose factorization machine using an FPGA.
