Figure 4
Performance of the machine for factorization compared to previous parallel update factorization machines. (a), 3-dimensional energy landscape of the N = 33,499 (241 × 139) factorization and an example of energy state during a single factorization operation. The energy states at the end of each iteration (left side) show that the probabilistic annealing enables frequent movement to the local minimums. In addition, the energy states of the last iteration (right side) show that the annealing process decreases the energy state dramatically and finally leads to the global ground. (b), Results of 4-bit to 64-bit factorization measurements of the previous works11,12 and the current work are shown. For a fair comparison between annealing schemes, performances without on-chip processing units are also shown. We repeated the experiment 1,000 times, and the number of sampling operations of the conventional sparse Ising machine12 is calculated using its 100% time-to-solution results. As shown in the graph, the probabilistic annealing achieved a performance improvement of up to 1.4 × 104 times at 30-bit factorization, and the digitally accelerated architecture reduced the number of sampling operations by 1.2 × 108 times than the previous work12 at 32-bit factorization. (c), Detailed factorization results from 50-bit to 64-bit with decision block are shown. Using the candidate sieve reduced the number of sampling operations at 50% accuracy by up to 66% (66% reduced at 52-bit factorization) with a small hardware cost. Detailed information about the sampling frequencies of these machines is provided in Methods.
