Table 2 Specific thermal resistances and thermal capacitances per unit area, illustrating that the decreased chip thickness from 350 to 110 μm has a minimal beneficial impact on the specific thermal resistance, whereas the adverse decrease of the thermal capacitance per unit area is proportional to the decreased chip thickness.

From: The effect of wafer thinning and thermal capacitance on chip temperature of SiC Schottky diodes during surge currents

Chip thickness

(μm)

Components of specific thermal resistance,\({{\varvec{R}}}_{{\varvec{s}}{\varvec{p}}-{\varvec{t}}{\varvec{h}}}\)

Total \({{\varvec{R}}}_{{\varvec{s}}{\varvec{p}}-{\varvec{t}}{\varvec{h}}}\)

(\({^\circ \mathrm{C}\, \mathbf{m}\mathbf{m}}^{2}/\mathbf{W}\))

110

\({R}_{sp-th (a)}=\frac{{t}_{SiC (a)}}{{k}_{SiC}}+\frac{{t}_{solder}}{{k}_{solder}}+\frac{{t}_{Cu}}{{k}_{Cu}}=0.22+0.83+2.03\)

3.1

350

\({R}_{sp-th (b)}=\frac{{t}_{SiC (b)}}{{k}_{SiC}}+\frac{{t}_{solder}}{{k}_{solder}}+\frac{{t}_{Cu}}{{k}_{Cu}}=0.71+0.83+2.03\)

3.6

Chip thickness (μm)

Thermal capacitance per unit area,\({C{\prime}}_{th}\)

Total \({C{\prime}}_{th}\) (\(\mathrm{J}/^\circ \mathrm{C}\, {\mathrm{m}}^{2}\))

110

\({{C}{\prime}}_{th \left(a\right)}= {\rho }_{SiC}{c}_{SiC}{t}_{SiC \left(a\right)}=3210\times 700\times 110\times {10}^{-6}\)

\(247.2\)

350

\({C{\prime}}_{th (b)}= {\rho }_{SiC}{c}_{SiC}{t}_{SiC (b)}=3210\times 700\times 350\times {10}^{-6}\)

\(786.45\)