Table 11 Error performance.

From: Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

Stages

25

26

Stages

Proposed

RMSE

Max(AE)

RMSE

Max(AE)

RMSE

Max(AE)

16

9.73E-04

7.98E-03

7.06E-04

3.80E-03

8

4.66E-04

2.76E-03

20

1.00E-04

8.70E-04

4.40E-05

2.27E-04

10

2.92E-05

1.70E-04

24

6.25E-06

4.97E-05

2.76E-06

1.49E-05

12

1.82E-06

1.03E-05

28

3.89E-07

3.21E-06

1.72E-07

9.02E-07

14

1.14E-07

6.69E-07

32

2.43E-08

2.14E-07

1.08E-08

5.68E-08

16

7.12E-09

4.13E-08

36

1.52E-09

1.33E-08

6.72E-10

3.54E-09

18

4.45E-10

2.59E-09

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