Table 12 Hardware complexity comparison to compute \(P^{1/N}\).

From: Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

Computation

25

26

Proposed

Stages

TC

RMSE

Stages

TC

RMSE

Stages

TC

RMSE

Log

25

182016

1.10E-06

22

155160

1.59E-06

10

102156

4.01E-07

Division

23

83904

1.12E-06

23

83904

1.15E-06

11

68288

1.11E-06

Exponentials

25

146952

1.67E-05

22

95760

1.29E-05

11

89340

1.21E-05

% Improvement

37.07

22.41

 
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