Table 13 Hardware complexity comparison to compute \(P^{N}\).

From: Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

Computation

25

26

Proposed

Stages

TC

RMSE

Stages

TC

RMSE

Stages

TC

RMSE

Log

24

126000

2.44E-06

22

113552

1.15E-06

10

78600

3.07E-07

Multiplier

1

31482

3.66E-06

1

31482

1.72E-06

1

31482

4.61E-07

Exponentials

27

257424

6.17E-05

22

95760

2.72E-05

11

89340

1.17E-05

% Improvement

51.94

17.18

 
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