Table 4 Selection criteria.

From: Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

\(\sigma _1\)

\(\sigma _0=2\)

\(\sigma _0=1\)

\(\sigma _0=0\)

\(\sigma _0=-1\)

\(\sigma _0=-2\)

\(Y_0,min\)

\(Y_0,max\)

Selection

criteria

\(Y_0,min\)

\(Y_0,max\)

Selection

criteria

\(Y_0,min\)

\(Y_0,max\)

Selection

criteria

\(Y_0,min\)

\(Y_0,max\)

Selection

criteria

\(Y_0,min\)

\(Y_0,max\)

Selection

criteria

2

2.546

2.698

2.625

0.970

1.054

1.012

0.182

0.233

0.207

− 0.291

− 0.261

− 0.275

− 0.606

− 0.589

− 0.59766

1

2.128

2.261

2.195313

0.738

0.812

0.773

0.043

0.087

0.063

− 0.375

− 0.348

− 0.359

− 0.653

− 0.638

− 0.64453

0

1.760

1.878

1.820313

0.533

0.599

0.566

− 0.080

− 0.041

− 0.063

− 0.448

− 0.425

− 0.438

− 0.693

− 0.680

− 0.6875

− 1

1.434

1.539

1.484375

0.352

0.410

0.383

− 0.189

− 0.154

− 0.172

− 0.513

− 0.492

− 0.500

− 0.730

− 0.718

− 0.72266

− 2

1.143

1.236

1.1875

0.191

0.242

0.219

− 0.286

− 0.255

− 0.270

− 0.571

− 0.553

− 0.563

− 0.762

− 0.752

− 0.75781