Figure 2
Multiplexer implementations for hybrid (a) XOR, (b) XNOR, (c) AND, (d) OR, (e) NAND, (f) NOR, and (g) generic logic gates.
Figure 2 | Scientific Reports
Multiplexer implementations for hybrid (a) XOR, (b) XNOR, (c) AND, (d) OR, (e) NAND, (f) NOR, and (g) generic logic gates.
