Figure 3 | Scientific Reports

Figure 3

From: Analog monolayer SWCNTs-based memristive 2D structure for energy-efficient deep learning in spiking neural networks

Figure 3

Device electrical characterization to confirm the analog switching behavior for the device resistance and capacitance. (a) 45 consecutive I–V sweeps from 4 to 22 V, the inset shows the multistate behavior under the application of consecutive threshold voltages. (b) 16 consecutive I–V sweeps from − 5 V to − 24 V. (c) and (d) represent the simultaneous Capacitance-Frequency and Conductance-Frequency measurements, respectively. Inset of (c) 11 consecutive I–V sweeps from 4 to 9 V. (e) and (f) Quantitative EDS analysis at LRS and HRS, respectively. (g) and (h) schematics to demonstrate the switching mechanism of the device. (h)-insets: I–V sweeps of the device after depositing new SWCNTs layer to retrieve the switching ability of the device, fitting results between the multistate switching characteristic presented by the SWCNTs-based memristor and Poole–Frenkel model. Drawings are prepared using Mindthegraph software and PowerPoint drawing tools.

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