Table 4 Hardware utilization, maximum speed, and average error of proposed Exp CORDIC implementations for different numbers of n_exp iterations.
Implementation in 11-bits | LUT | Register slice | DSP | Max speed | Average error |
|---|---|---|---|---|---|
Exp CORDIC with 2 iterations | 330 | 0 | 0 | 768 MHz | 6.76 × 10–2 |
Exp CORDIC with 3 iterations | 370 | 0 | 0 | 769 MHz | 1.83 × 10–2 |
Exp CORDIC with 4 iterations | 370 | 0 | 0 | 769 MHz | 5.67 × 10–3 |
Exp CORDIC with 5 iterations | 326 | 0 | 0 | 768 MHz | 5.63 × 10–3 |
Exp CORDIC with 6 iterations | 330 | 0 | 0 | 685 MHz | 6.44 × 10–3 |
Exp CORDIC with 7 iterations | 349 | 0 | 0 | 685 MHz | 1.00 × 10–2 |
