Figure 4 | Scientific Reports

Figure 4

From: Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads

Figure 4

Memory operation and signalling schemes: (a) Write and read operation schemes in crossbar array. Timing diagram for (b) FeCap and (c) FeFET. Programming the FeCap requires an operating voltage of 1.2 V, whereas the FeFET programs at 3 V. The change in the polarization state controls the value of capacitance in FeCap and the value of conductance in FeFET.

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