Figure 5 | Scientific Reports

Figure 5

From: Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads

Figure 5

(a) FeCap-based IMC crossbar architecture for MVM computations. (b) Simulation results depicting the accumulated analog MVM (or MAC) output for \(8 \times 8\) array, where FeCaps programmed to HCS and a number of WL (input) activations are varied. (c) Timing diagram for a \(4\times 4\) array to show the operation of crossbars, illustrating the different scenarios that lead to erroneous calculations, which result from the inherent low HCS/LCS ratio.

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