Figure 7
From: Floating body effect in indium–gallium–zinc–oxide (IGZO) thin-film transistor (TFT)
The schematics of (a) bias condition (VGS and VDS), ID, and hole concentration of SOI MOSFET with the initial pulse and the next pulse applied with short delay time (green line) and long delay time (indigo line), (b) FBE in SOI MOSFET at the t1 which occurs regardless of delay time. The schematics of SOI MOSFET during the (c) short delay time (t2) and (d) long delay time (t3).
