Fig. 3
The proposed ASDB layouts for (a) AND, (b) NAND, (c) OR, (d) NOR, (e) XOR, and (f) XNOR gates using SiQAD with \({\epsilon _r}\) = 5.6 and \({{{\varvec{\uplambda}}}_{TF}}\)= 5 nm.
Fig. 3 | Scientific Reports
The proposed ASDB layouts for (a) AND, (b) NAND, (c) OR, (d) NOR, (e) XOR, and (f) XNOR gates using SiQAD with \({\epsilon _r}\) = 5.6 and \({{{\varvec{\uplambda}}}_{TF}}\)= 5 nm.
