Table 5 Comparison of the proposed NC SOI FET with the literature.

From: Engineering the ferroelectric polarization to optimize the GIDL and negative output conductance in negative capacitance FET

Device type

Methodology

L (nm)

TFE (nm)

ION (mA/µm)

ION/IOFF

NOC optimized/mitigated

GILD effect

NC SOI FET12

Pr = 6 µC/cm2 & Ec = 3 MV/cm

20

4

~ 0.8

~ 106

Yes

Not analyzed

NC SOI FET22

FE layer at BOX &gate oxide

20

3

1.18

~ 105

Yes

Not analyzed

NC SOI FET22

FE layer at gate oxide

20

3

1.05

~ 107

No

Not analyzed

NC SOI FET19

With TFE variation

20

7

~ 2.5

~ 106

No

Not analyzed

NC SOI FET19

With TFE variation

20

1.7

~ 1

~ 105

Yes

Not analyzed

NC SOI FET (SM)

This work

22

7

0.674

~ 106

No

Analyzed

NC SOI FET (LɸM1:LɸM2 of 1:1)

This work

22

7

0.818

~ 106

Yes (optimized)

Analyzed & optimized

NC SOI FET (LɸM1:LɸM2 of 1:2)

This work

22

7

0.824

~ 106

Yes (mitigated)

Analyzed & optimized