Fig. 5
(a) Karnaugh map for extracting logical relationships, (b) The logic circuit of the full adder at the gate level, (c) Full adder logic circuit at the transistor level.
Fig. 5 | Scientific Reports
(a) Karnaugh map for extracting logical relationships, (b) The logic circuit of the full adder at the gate level, (c) Full adder logic circuit at the transistor level.
