Table 4 a. Comparing the suggested Dadda 8-bit current mode approximation multipliers with existing architecture.

From: Energy efficient approximate compressor architectures for high performance image multiplication in CNTFET technology

power (µW)

Maximum of delay (ns)

PDP (ns × µW)

 

Proposed multiplier(8-bit)

6.73

0.183

1.23

Proposed multiplier(16-bit)

33.37

0.947

31.6

[10]

11.96

0.454

5.43

[36]

8.1

0.565

4.5

[37]

10.09

0.625

6.3

[19]

51.1

0.33

16.83

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