Table 20 Sensitivity to stress-threshold design (8 × 8, 10% faults).

From: Fault tolerant and quality of service aware routing algorithm based on priority technique for scalable network on chip architectures

Design

Thresholds (Low/Mod/Sev)

Throughput

Delay

Baseline (3-level)

< 0.47 / 0.47–0.87 / >0.87

5.08

41

3-level (tighter mid/high)

< 0.45 / 0.45–0.85 / >0.85

5.05

41

3-level (more conservative)

< 0.50 / 0.50–0.90 / >0.90

5.02

42

5-level (finer bins)

< 0.25 / <0.50 / <0.75 / <0.90 / ≥0.90

5.10

41

Continuous (EWMA, α = 0.2)

n/a (continuous sts_t)

5.12

40

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