Fig. 6

(a) The Cole–Cole plots of B-doped Si wafers etched for 5, 15, 20 and 25 min (inset is the equivalent circuit) and (b) 10 min.

(a) The Cole–Cole plots of B-doped Si wafers etched for 5, 15, 20 and 25 min (inset is the equivalent circuit) and (b) 10 min.