Fig. 4
Mapping a Two-Linked IK problem graph onto a quantum annealer’s hardware architecture–highlighting the embedding of a densely connected problem graph (left) onto the physical qubit connectivity of a D-Wave quantum processing unit (right). The yellow arrows illustrate the correspondence between logical nodes and their mapped qubits, while the red and green edges represent couplings between qubits in the hardware graph. The white nodes on the left figure and the right figure represent zeroes in the QUBO and Ising formulations, respectively, while the yellow and blue nodes represent ones in the QUBO and Ising formulations, respectively.
