Table 3 The post-layout simulation results of different nvSRAM cells in the 4 Kb memory array.
From: Dual-directional CIM-based non-volatile SRAM for instant-on/off energy-constrained edge AI devices
Parameters | I-MTJ | P-MTJ | Proposed | ||
|---|---|---|---|---|---|
HSNM (mV) | 217 | 221 | 219 | 219 | 222 |
Half-select (mV) | 54 | 57 | 51 | 56 | 110 |
RSNM (mV) | 54 | 57 | 51 | 56 | 222 |
WSNM (mV) | 208 | 217 | 224 | 225 | 372 |
Read delay (ps) | 10.9 | 10.5 | 10.7 | 10.4 | 38.2 |
Read power (µW) | 572.7 | 76.4 | 500.3 | 150.0 | 36.4 |
Read PDP (fJ) | 6.2 | 0.8 | 5.4 | 1.6 | 1.4 |
Write delay (ps) | 11.9 | 10.9 | 11.6 | 8.8 | 31.8 |
Write power (µW) | 333.8 | 44.6 | 292.5 | 91.9 | 11.0 |
Write PDP (fJ) | 4.0 | 0.5 | 3.4 | 0.8 | 0.3 |
Leakage power (µW) | 813.4 | 105.6 | 668.4 | 214.1 | 164.2 |
Bit cell area (µm2) | 0.218 | 0.141 | 0.260 | 0.076 | 0.186 |
