Table 4 The post-layout simulation results of the store and restore operations in the 4 Kb memory array.

From: Dual-directional CIM-based non-volatile SRAM for instant-on/off energy-constrained edge AI devices

Desings

14

I-MTJ

15

P-MTJ

15

13

Proposed

Store

Delay (ns)

6.3

4.0

2.8

2.6

3.4

Power (µW)

193.0

46.9

49.9

147.4

5.9

PDP (pJ)

1.21

0.19

0.14

0.38

0.02

Restore

Delay (ps)

2008

1002

17.2

88.5

46

Power (µW)

556.8

65.5

406.3

2.8

91.6

PDP (fJ)

1118.0

65.6

6.98

0.25

4.21

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