Table 5 Post-layout evaluation of the designs for implementing sAlexNet under power failure conditions on layer 4.

From: Dual-directional CIM-based non-volatile SRAM for instant-on/off energy-constrained edge AI devices

Designs

Delay (ms)

Power (mW)

EDP (µJ s)

47

100.7

1.17

117.82

48

98.7

1.32

130.28

49

100.4

1.31

131.52

Proposed

108.4

0.66

71.54

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