Fig. 1 | Scientific Reports

Fig. 1

From: MicroNAS for memory and latency constrained hardware aware neural architecture search in time series classification on microcontrollers

Fig. 1

MicroNAS requires the dataset to be split into three different sets which are used at different stages in the pipeline. The user specifies the dataset to be used, the target MCU (\(MCU_t\)) and the maximum allowed hardware utilization in terms of execution latency (\(Lat_t\)) and peak memory consumption (\(Mem_t\)). Output of the system is a corresponding neural network in the tf-lite format.

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