Table 1 Structural description of the proposed Dl-FG-ME-TFET.

From: Energy-efficient neuromorphic system using novel tunnel FET based LIF neuron design for adaptable threshold logic and image analysis applications

S. no.

Parameter

Specifications

1

Gate length (\(L_G\))

20 nm

2

S/D length 2

18 nm

3

Floating gate length

2 nm

4

InGaAs and silicon thickness

8 nm

5

\(HfO_2\) thickness

2 nm

6

Source work-function

5.9 eV

7

Drain work-function

3.9 eV

8

Gate work-function

4.9 eV

9

Floating gates work-function

3.4 eV