Fig. 7 | Scientific Reports

Fig. 7

From: Device grade solid-state pouch and coin cell supercapacitors dual assembly using consumed battery waste to best utilization

Fig. 7

(a) Schematic of solid-state pouch cell, (b) specific and areal capacitance of solid-state pouch cell at different scan rates (inset: cyclic voltammetry in the scan rate ranging from 5 to 100 mV s-1), (c) galvanostatic charge discharge plot at different current densities, (d) specific and areal capacitance at different current of solid-state pouch cell, and (e) Nyquist plot of solid-state pouch cell (inset: equivalent circuit),

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