Fig. 1
From: Mitigating side channel attacks on FPGA through deep learning and dynamic partial reconfiguration
The architecture of Mitigating the SCA using the DL and DPR.
Fig. 1 | Scientific Reports
From: Mitigating side channel attacks on FPGA through deep learning and dynamic partial reconfiguration
The architecture of Mitigating the SCA using the DL and DPR.
