Abstract
This study aims to investigate the influence of parasitic capacitances within half-bridge SiC power metal oxide semiconductor field effect transistor (MOSFET) modules, including input capacitance (Ciss), output capacitance (Coss), and reverse transfer capacitance (Crss), on their switching transients and switching losses during dynamic switching. A secondary objective is to assess the impact of parasitic capacitances on power loss and thermal performance in a single-phase SiC MOSFET inverter operating in an H-bridge configuration that employs two half-bridge SiC power MOSFET modules identical to the one described above. To accurately capture the switching transients, switching losses, and parasitic effects of the SiC power module during dynamic transients and inverter operating under sinusoidal pulse-width modulation (SPWM) in single-phase open-loop mode, an electromagnetic-circuit modeling (EMCM) framework is developed. This approach integrates an electromagnetic model, an equivalent circuit model, and a SiC MOSFET characteristic model. The validity of the proposed integrated modeling framework is verified by comparison with the measurement results obtained from double-pulse testing (DPT) and thermal resistance experiments. Ultimately, using the developed integrated modeling framework, a guideline for improving power loss and thermal behavior of the power inverter under various device and system conditions is formulated through parametric analysis. The findings demonstrate that parasitic capacitances significantly affect switching waveforms and loss, and also influence the thermal performance of the system, with Crss showing the most dominant impact.
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The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.
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Funding
This work is partially supported by National Science and Technology Council (NSTC), Taiwan, ROC, under Grant no. NSTC 112-2221-E-035-076-MY3 and NSTC 113-2221-E-035-031-MY3.
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Conceptualization, H.-C.C., W.-Y.J. and T.-C.C.; methodology, H.-C.C., C.-F.Y. and W.-Y.J.; software, W.-Y.J.; validation, H.-C.C., W.-Y.J., Y.-C.L. and P.-K.C.; formal analysis, W.-Y.J. and Y.-C.L.; investigation, H.-C.C., W.-Y.J., Y.-C.L. and P.-K.C.; resources, H.-C.C., C.-F.Y. and T.-C.C.; data curation, W.-Y.J. and Y.-C.L.; writing—original draft preparation, H.-C.C. and T.-C.C.; writing review and editing, H.-C.C., C.-F.Y. and T.-C.C.; visualization, W.-Y.J. and C.-F.Y.; supervision, H.-C.C.; project administration, H.-C.C. and T.-C.C.; funding acquisition, H.-C.C., C.-F.Y. and T.-C.C. All authors have read and agreed to the published version of the manuscript.
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Cheng, HC., Jhu, WY., Liu, YC. et al. Effects of parasitic capacitance on switching transients and thermal performance in a single-phase SiC power MOSFET inverter. Sci Rep (2026). https://doi.org/10.1038/s41598-026-44458-9
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DOI: https://doi.org/10.1038/s41598-026-44458-9
