Fig. 1
From: Benchmarking engineered exchange interactions on NISQ hardware
Hardware-aware quantum circuit implementations of engineered exchange interactions (\(i\textrm{SWAP}\) and \(\sqrt{i\textrm{SWAP}}\)). (a) Decomposition of the \(i\textrm{SWAP}\) gate into the native gate set \(\{\texttt {CNOT}, \texttt {RZ}, \texttt {SX}\}\) using two CNOT gates interleaved with single-qubit \(R_Z\) and \(\textrm{SX}\) (\(\sqrt{X}\)) rotations. The matrix definitions are \(\textrm{SX} = \begin{pmatrix} \frac{1}{2}(1+i) & \frac{1}{2}(1-i) \\ \frac{1}{2}(1-i) & \frac{1}{2}(1+i) \end{pmatrix}\) and \(R_Z(\gamma ) = \begin{pmatrix} e^{-i\gamma /2} & 0 \\ 0 & e^{i\gamma /2} \end{pmatrix}\). (b) Decomposition of the \(\sqrt{i\textrm{SWAP}}\) gate using the same native gate set, also requiring only two CNOT gates. Both compilations minimize two-qubit interactions to reduce error accumulation on NISQ hardware.
