Fig. 5 | npj 2D Materials and Applications

Fig. 5

From: An atom-to-circuit modeling approach to all-2D metal–insulator–semiconductor field-effect transistors

Fig. 5

Equations (F1)–(F5) are mathematical expressions for the proposed compact device model. The closed form expressions of dc drain current IDC and terminal charges viz. QG, QD, QS are obtained employing piecewise charge linearization technique. Inset: SPICE engine assigns terminal voltages (viz. VG, VD, and VS) to the Verilog-AMS module, which computes terminal currents (viz. iG, iD, and iS) according to Eqn. (F1)–(F5), and then returns them to the individual terminals to be processed by the SPICE engine

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