Fig. 4
From: Large-signal model of 2DFETs: compact modeling of terminal charges and intrinsic capacitances
Intrinsic capacitances versus a overdrive gate bias (at Vds = 1 V) and b drain bias (at Vgs – Vg0 = 3.4 V). Solid lines represent our model outcome and dashed lines show the data calculated using the model adopted in ref. 2
