Fig. 2: Hidden layer neuron block and its equivalent MOS architecture. | npj 2D Materials and Applications

Fig. 2: Hidden layer neuron block and its equivalent MOS architecture.

From: Hybrid architecture based on two-dimensional memristor crossbar array and CMOS integrated circuit for edge computing

Fig. 2: Hidden layer neuron block and its equivalent MOS architecture.The alternative text for this image may have been generated using AI.

a Block diagram representation of a hidden node implementing 9D Gaussian cell using 2D NP Gaussian cells. b Block level representation of a generic 2D NP Gaussian cell made by cascading N and P-type Gaussian cells and current mirrors. c MOS structure of P-type Gaussian cell. d MOS structure of N-type Gaussian cell. e Layout of a single hidden layer node in Fig. 2a implementing 9D Gaussian cell using 180 nm CMOS TSMC technology.

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