Fig. 3: KPFM characteristics to reveal intercoupled polarization and memory behavior.

Surface potential mapping of the fabricated FET for (a) −V_G, (b) 0 V_G, and (c) +V_G, showing the spatial potential distributions across different materials. The metal (M) and the two types semiconducting regions (In₂O₃ and In₂Se₃) and the polarization directions are marked accordingly. The schematic crystal structures exhibit the position of In and Se atoms for (d) negative and (e) positive gate-induced polarization. The intercoupled polarization (brown arrows) and the in-plane (E_IP), and out-of-plane (E_OOP) electric field (green arrows) directions are marked for better visualization. f Surface potential line profiles across the FET channel for different gate-bias voltages (the regions of the respective materials are separated by green vertical dotted lines). The change in potential slope with applied gate-bias voltage indicates the dipole rotation. g In-plane electric field at the middle of In₂O₃ and In₂Se₃ for a complete cycle of applied gate voltage (see Supplementary Fig. 4). A distinct potential slope, as well as remnant hysteresis nature (arrows indicate the gate sweep direction), is observed for the In₂Se₃ region, while no hysteresis recorded for In₂O₃. The minor change in potential slope in In₂O₃ is attributed to tip-sample averaging effect. h Energy barrier across all types of interfaces in the FETs as a function of gate-bias voltage. For positive gate voltage, the potential barrier for Au/In₂O₃ interfaces become constant but increases with negative gate voltage. In contrast, potential barrier between In₂Se₃/Au changes its polarity due to ferroelectric dipoles induced charge reversal. The energy barrier across the HJ interface increases monotonically throughout the measurement range.