Fig. 1: Schematic and process flow of the 3D Si-MoS2 CMOS inverter.
From: Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET
a Completed Si FinFET on SiO2/Si substrate. b Deposition of SiO2 via PECVD to create an intermediate layer on the FinFET for passivation, followed by chemical mechanical polishing for the thinning and flattening of the SiO2 layer. c Building the monolithic intertier vias (MIVs) by employing contact hole etching and e-beam vapor deposition. d Transferring the monolayer MoS2 triangles on the SiO2 layer. e Fabrication of source/drain electrodes connected to MoS2 using e-beam lithography and e-beam vapor deposition. f E-beam vapor deposition of Al2O3 dielectric as the top-gate on MoS2. g Schematic of a CMOS inverter fabricated by vertically integrating a p-channel Si FinFET and an n-channel monolayer MoS2 transistor. The inset shows the cross-sectional structure of the Si FinFET. h SEM image of the Si FinFET. Scale bar: 100 μm. i TEM image showing the cross-section of Si FinFET. Scale bar: 25 nm. j Optical image showing the top view of the fabricated 3D CMOS inverter. Scale bar: 100 μm. k Zoom-in image showing the MoS2 FET in k. Scale bar: 10 μm.
