Fig. 4: Electrical characteristics of top-gated MoS2 FET on upper-tier and lower-tier Si FinFET.
From: Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET
Measured transfer characteristics of a a top-gate MoS2 FET on intermediate SiO2 layer and b a Si FinFET on Si/SiO2 (VDS = 0.05 V and 1.00 V). For the Si FinFET, the measurement was conducted before and after the MoS2 FET fabrication. In a and b, the gate current (IGS) was measured to acquire the level of the leakage current in the fabricated transistors. c Schematic of the top-gated MoS2 FET. The TEM image shows the cross-section of the top-gated MoS2 FET. Scale bar, 10 nm.
