Fig. 5: Output characteristics of 3D Si-MoS2 complementary inverter.
From: Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET
a Voltage transfer characteristics of the 3D CMOS inverter for power supply voltage (VDD) from 0.1 V to 2.1 V in 0.5 V steps. Peaks in the red curves indicate the corresponding voltage gain at different VDD. b Noise margin of a CMOS inverter. When the inverter was applied with a low input voltage, the noise margin low (NML) is 0.449 VDD (VDD = 2.1 V). When applied with a high input voltage, the inverter has a noise margin high (NMH) of 0.370 VDD (VDD = 2.1 V).
