Fig. 6: Impact of annealing on the hysteresis dynamics. | npj 2D Materials and Applications

Fig. 6: Impact of annealing on the hysteresis dynamics.

From: Variability and high temperature reliability of graphene field-effect transistors with thin epitaxial CaF2 insulators

Fig. 6

Double sweep ID-VG characteristics measured for our Batch#1 GFETs at T = 25 oC, 175 oC and 25 oC after annealing using S = 0.002 V s−1. Just after 10 min of ambient exposure, Device A (a) exhibited counterclockwise and Device B (b) clockwise hysteresis. c At 100 oC and at 175 oC the counterclockwise hysteresis in Device A is strongly suppressed, and after annealing at 175 oC both devices exhibit similar clockwise hysteresis (d). e, f The corresponding results for a Batch#2 GFET which show no counterclockwise contribution and conventional thermal activation of charge trapping. These GFETs experienced an initial annealing of 2 days at 100 oC and 5 h at 175 oC prior to the first measurement round.

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