Table 1 Key device parameters for 2D-channel DG FeFET used in this work to describe sub-2nm technology node
Parameter | Channel materials – Technical node | |||
|---|---|---|---|---|
Si FinFET - 3 nm | Si GAAFET - 2 nm | WS2 DGFET - Sub-2nm (this work) | ||
Dimension | Contacted poly-gate pitch (CGP) | 48 nm | 45 nm | 42 nm |
Metal pitch (MP) | 24 nm | 20 nm | 16 nm | |
Gate length (LG) | 16 nm | 14 nm | 14 nm | |
Channel width (WCH) | 101 nm | 216 nm | 52 nm | |
Spacer length (LSPC) | 6 nm | 6 nm | 8 nm | |
Source/Drain contact length (LSD) | 20 nm | 19 nm | 12 nm | |
Interfacial layer thickness (TIL or EOT) | 0.5 nm | 0.5 nm | 0.5 nm | |
Source/Drain extension region doping concentration | 1021–1022 cm−3 | 1021–1022 cm−3 | 4 × 1020 cm−3 | |
Spacer dielectric constant | 3.5 | 3.3 | 7.5 | |
Interfacial layer dielectric constant | 3.9 | 3.9 | 3.9 | |
Electrical property | Supply voltage (Vdd) | 0.70 V | 0.65 V | 0.5 V |
Effective Mobility | 125 cm2/V·s | 100 cm2/V·s | 200 cm2/V·s | |
On current | 874 μA/μm | 787 μA/μm | 1.1 mA/μm | |
Contact resistance @ 300 K | 1 × 10−9 Ω cm2 | 1 × 10−9 Ω cm2 | 1.8 kΩ μm | |
