Fig. 2: Integration process of Si-MBC FETs and transition challenges for 2DM-MBC FETs. | npj 2D Materials and Applications

Fig. 2: Integration process of Si-MBC FETs and transition challenges for 2DM-MBC FETs.

From: Enabling the Angstrom Era: 2D material-based multi-bridge-channel complementary field effect transistors

Fig. 2

The left panel illustrates the requirements of conventional integration process for Si-based MBC FETs, which includes four main steps: (i) large-area and high-quality epitaxial growth of Si/SiGe stacks, (ii) selective etching to create stable, free-standing Si channels, (iii) formation of a high-quality gate structure surrounding the channel, and (iv) low-resistance source/drain contacts and doping compatible with CMOS. The right panel highlights the specific challenges of adapting this process for 2DM-based MBC FETs and proposes potential solutions. Key challenges in adapting Si process to 2DMs are highlighted: (i) achieving wafer-scale, single crystalline epitaxial growth of 2DMs at low temperature, (ii) maintaining stable free-standing and damage-free 2DM channels during the release process, (iii) depositing high-k dielectrics on 2DM surfaces and controlling interfacial stability, and (iv) developing CMOS-compatible doping and low contact resistance techniques for 2DMs. The right panel outlines potential solutions to these challenges.

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