Fig. 4: Integration challenges of sequential and monolithic CFET architectures. | npj 2D Materials and Applications

Fig. 4: Integration challenges of sequential and monolithic CFET architectures.

From: Enabling the Angstrom Era: 2D material-based multi-bridge-channel complementary field effect transistors

Fig. 4

Technical challenges are addressed in device performance, thermal management, process integration, and manufacturing complexity for both architectures. The top panel depicts the challenges associated with sequential CFETs, including (i) high process costs, (ii) limited thermal budget, (iii) wafer bonding defects, (iv) misalignment between top-tier and bottom-tier devices, and (v) wide isolation between P and N devices. The lower panel shows the challenges of monolithic CFETs, which include (i) limited design flexibility, (ii) difficulty in separating threshold voltages for P and N transistors, (iii) high aspect ratio structures, (iv) challenges in ensuring electrical isolation between P and N devices, and (v) increased contact resistance in bottom devices.

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