Fig. 6: Schematic illustration and operational characteristics of devices based on 2D Lateral Heterostructure geometry.
a Schematic of an external thermal measurement circuit based on a MoSe2-WSe2 LHS. V1 and V2 measure the voltage of the two gold sensors (Au), while I1 and I2 measure the current in each loop. The blue and red arrows indicate the thermal conductivity directions, J+ from MoSe2 to WSe2 and J- from WSe2 to MoSe2, respectively, reproduced from ref. 119 with permission from Science Publishing. b Device schematic for LHS-based tunneling field effect transistors (LHS-TFET) and vertical heterostructure TFETs (VH-TFET), illustrating the band profile in the ON and OFF states. Key figures of merit, including on-state current (Ion), off-state current (Ioff), tunneling efficiency, etc., are tabulated to emphasize performance metrics. c Schematic representation of LHS-based heterojunction bipolar transistor (HBT) along with the typical current–voltage (I–V) characteristics (citation with copyright). The figures of merit, including the cut-off frequency, base transit time, injection efficiency, base transport factor, current gain, and cut-off frequency, are required parameters for high-speed and high-frequency performance, reproduced from ref. 143 with permission from ACS Publishing.
