Extended Data Fig. 3: Threshold voltage stability.

a, Schematics of the gate lag measurement employed to determine the device V_TH stability. First, the device is stressed for a time t_off = 5 ms during which a quiescent gate voltage V_G,q is applied to cause trapping in the gate stack. The quiescent drain voltage V_D,q is 0 V to avoid any drain lag contribution or device heating. Then the gate voltage V_G is set to 7 V and the drain voltage V_D to 1 V for a short time t_on = 5 μs, during which the drain current (I_D) is measured. Trapping in the gate stack and instability of the device V_TH result in a variation of the measured I_D depending on the value of the applied V_G,q. b, Gate lag measurement as a function of V_G,q for the presented multi-channel devices, and for a reference single-channel device having similar V_TH. The measured I_D has been normalized to the value obtained at V_G,q = 7 V, that is when the gate voltage is kept constant and thus no stress is applied. A negligible gate lag effect is observed for the multi-channel devices with a current reduction of less than 4 % in the whole measurement range, which proves their excellent V_TH stability. Moreover, multi-channel devices show much-reduced gate lag with respect to the single-channel references, which instead present a current decrease of 20 % at V_G,q of −3 V. Such behavior is due to the multi-channel larger carrier concentration which results in a weaker influence of the traps in the gate dielectric on the device V_TH. c, V_TH as a function of temperature (T) for the presented multi-channel devices. A very constant V_TH behavior can be observed in the whole measurement range up to 150 °C with the device maintaining full E-mode operation and showing only a minor V_TH shift of 50 mV.