Extended Data Fig. 4: Current collapse in multi-channel tri-gate HEMTs.
From: Multi-channel nanowire devices for efficient power conversion
a, Schematics of the double pulse measurement employed to determine the device current collapse. The device is first stressed in the off-state for a time toff = 5 ms at a large quiescent drain bias VD,q, and then it is suddenly turned on for a short time ton = 50 μs during which its on-resistance is measured. b, Normalized RON,dyn as a function of VD,q for the multi-channel devices and for two different single-channel reference devices, cofabricated in the same batch, with (1) gate termination in the nanowire region and same design with respect to the multi-channel case (2) gate termination on the planar region as for conventional single-channel device architectures. All devices present a low-pressure chemical vapor deposition (LPCVD) Si3N4 passivation layer. Single-channel devices with the gate termination in the nanowire region show a highly degraded RON,dyn as a consequence of the increased surface area at the nanowire sidewalls, which result in more severe electron trapping during the off-state stress. This is not the case, instead, for multi-channel devices, whose much larger carrier density (Ns) and 3D structure considerably reduce the virtual gate effect due to sidewalls traps. Most importantly, multi-channel devices show very similar performance with respect to conventional single-channel devices with gate termination on the planar region, which represents the optimal architecture for such single-channel heterostructures. This demonstrates that multi-channel devices can be effectively passivated despite their 3D architecture and can provide not only outstanding DC performance but also excellent dynamic behavior.
