Fig. 6: Long-term electrical stability assessed using BTI.
From: Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning
In BTI measurements, the FET is subjected to extended periods of elevated gate bias and the drifts in the Dirac voltage during the degradation and recovery periods are recorded. a, Type 1 device subjected to –10 V for 1 ks. b,c, Type 1 FET is subjected for increasing time spans to elevated NBTI gate bias of –10 V (b), resulting in a larger degradation than observed for the same conditions on Type 2 FETs (c). d–f, When applying an elevated PBTI voltage level of 10 V to the GFETs (d), the Dirac voltage of Type 1 devices drifts more and barely recovers (e) compared with their Type 2 counterparts (f). To avoid an impact of the measurement history, the measurements shown were performed on different devices.
