Fig. 1: Challenges of applying 2D RRAM to large 3D CNNs and proposed 3D nvCIM scheme.
From: A computing-in-memory macro based on three-dimensional resistive random-access memory
a, Challenge of more area due to more weights, multibit weight representation and wider metal wire. b, Challenges of readout current IBL overlap and conflict between low power and low latency. c, Proposed high-precision nvCIM scheme based on MLSS 3D VRRAM. ADINWM scheme with the aid of CADS circuits can effectively alleviate IBL overlap caused by the conventional PWIVMM scheme and improve the inference accuracy. The implementation of the CIM macro based on the integrated 3D VRRAM chip elaborates a complete solution to execute CNN edge computing.
