Fig. 2: 3D VRRAM-based nvCIM macro using ADINWM scheme.
From: A computing-in-memory macro based on three-dimensional resistive random-access memory
a, Data flow and architecture of the conventional PWIVMM scheme for 1bIN–1bPW VMM operation (red lines) and the ADINWM scheme for 8bIN–8bPW VMM operation (blue lines). The dotted lines show the corresponding data flow of the 1bIN–1bNW and 8bIN–8bNW operations in the NWL. b, Implementation framework of the conventional PWIVMM scheme and proposed ADINWM scheme. The macro can be configured as the 1bIN–2bW, 4bIN–5bW and 8bIN–9bW operations based on the ADINWM scheme. As a comparison, it also realizes the 1bIN–2bW operation using the PWIVMM scheme. c, Formula and table of the 8bIN–8bPW operation in the PWL. The result takes the difference with the result of the 8bIN–8bNW operation in the NWL to get the result of the 8bIN–9bW operation. The 4bIN–5bW operation is similar to the 8bIN–9bW operation (Supplementary Fig. 2).
