Fig. 3: CADS circuit for error mitigation.
From: A computing-in-memory macro based on three-dimensional resistive random-access memory
a, Schematic of the CADS circuit. Here N is the normalized width of the CMOS transistor. b, Initial readout current IBL distribution and the current distribution after shaping by the CADS circuit. The variation in IBL leads to a decrease in the inference accuracy on the dataset. This scheme enlarges the SM to 5 nA. Stable IBL after shaping can improve the inference accuracy. c, Operations and waveform of the CADS circuit. At the beginning of each cycle, the CADS circuit can convert IBL in a certain range to a fixed value.
