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A CMOS-integrated spintronic compute-in-memory macro for secure AI edge devices

Nature Electronics volume 6, pages 534–543 (2023)Cite this article

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Abstract

Artificial intelligence edge devices should offer high inference accuracy and rapid response times, as well as being energy efficient. Ensuring the security of these devices against malicious attacks and illegal access requires data protection mechanisms and secure access control. Here we report a spintronic non-volatile compute-in-memory macro for efficient dot-product edge computing with secure access control for activation, key and data protection against power-on and power-off probing. The approach relies on spintronic-based physically unclonable functions and two-dimensional half-complement physical encryption, as well as a snoop-proof self-decryption burst-read scheme in conjunction with a sparsity-and-rectified-linear-unit-aware early-termination compute-in-memory engine. The 6.6 megabit complementary metal–oxide–semiconductor (CMOS)-integrated macro uses 22 nm spin-transfer torque magnetic random-access memory technology. The macro achieves high randomness (inter-Hamming distance, 0.4999) and high reliability for physically unclonable functionality (intra-Hamming distance, 0), as well as a high energy efficiency for dot-product computation (between 30.1 and 68.0 tera-operations per second per watt).

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Fig. 1: Overview of 6.6 Mb STT-MRAM nvCIM macro.
Fig. 2: SRR-PUF.
Fig. 3: 2DHC-PE and SP-SDBR schemes.
Fig. 4: SRET-CIME.

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Data availability

The data that support the plots presented in this paper as well as other findings derived from this study are available from the corresponding author upon reasonable request.

Code availability

The code that supports the experiment platforms is available from the corresponding author upon reasonable request.

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Acknowledgements

We express our appreciation for support from NTHU, TSMC and NSTC, Taiwan.

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Authors and Affiliations

  1. National Tsing Hua University (NTHU), Hsinchu, Taiwan, Republic of China

    Yen-Cheng Chiu, Chia-Sheng Yang, Shih-Hsin Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang & Meng-Fan Chang

  2. Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, Republic of China

    Win-San Khwa, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang & Meng-Fan Chang

  3. National Chung Hsing University (NCHU), Taichung City, Taiwan, Republic of China

    Mon-Shu Ho

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Contributions

Y.-C.C. designed the circuits for the nvCIM macro and test chip. Y.-C.C., W.-S.K., C.-S.Y., S.-H.T., H.-Y.H., F.-C.C., Y.W., Y.-A.C., F.-L.H., C.-Y.L., G.-Y.L., P.-J.C., T.-H.P., C.-C.L., R.-S.L., C.-C.H., K.-T.T., M.-S.H. and M.-F.C. contributed ideas. C.-S.Y., S.-H.T., H.-Y.H., F.-C.C., Y.W., Y.-A.C., F.-L.H., C.-Y.L., G.-Y.L., P.-J.C. and T.-H.P. built the test measurement system and testing flow for the STT-MRAM nvCIM macro. F.-C.C., Y.W., G.-Y.L. and C.-Y.L. conducted the security experiment and AI demonstration system. Y.-C.C. performed the analysis and measurements of the nvCIM macro. C.-P.L., Y.-D.C., T.-Y.J.C. and M.-F.C. managed the project. Y.-C.C., M.-S.H. and M.-F.C. wrote the paper.

Corresponding author

Correspondence to Meng-Fan Chang.

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Extended data

Extended Data Fig. 1 Experiment platform used to assess AI inference operations of the nvCIM macro with Resnet20 model.

a, Experiment platform including nvCIM testchip, FPGA board as system controller with intermediate data processor, and a PC to display classification results on an LCD screen. This nvCIM test-chip eliminated the drop in inference accuracy typical of software-based inference, regardless of the dataset SVHN, CIFAR-10, BraTS, and CIFAR-100. b, Flow chart showing inference process implemented on experiment platform. The nvCIM macro performed full-channel dot-product operations (convolutions), while the FPGA fed the input to the nvCIM macro, collected the full-channel dot-product values (Dot-PVFC) from the nvCIM macro, performed pooling operations, and executed the 1st-layer convolution operation. The PC platform presented intermediate data generated during inference and the final inference results on an LCD screen.

Extended Data Fig. 2 Experiment involving chip-ID identification using the nvCIM macro.

a, This experiment was implemented using an nvCIM test-chip, an FPGA as a system controller, and a PC to display chip-ID comparison results. b, Flow chart of chip-ID identification operation. The 6.6 Mb nvCIM macro created a chip-ID, while the FPGA fed the challenge to the nvCIM macro and collected the chip-ID. The nvCIM macro verified the chip-ID, while the FPGA fed the challenge and external chip-ID (chip-IDE) and stored the chip-ID comparison results. The PC was used as a command interface presenting the comparison results and chip-IDs on the LCD screen.

Extended Data Fig. 3 Experiment on accessing secured data using the nvCIM macro.

a, Fabricated 22 nm 6.6 Mb nvCIM test-chip used with an FPGA as system controller and PC to display the comparison results of accessing the secured data on an LCD screen. b, Flow chart showing the process by which secured data was accessed, wherein the FPGA fed the challenge, write command, and owner-KEY to the nvCIM macro, which subsequently performed a secure data-write operation. The data-read operation involved the FPGA feeding the challenge, read command, and user-KEY to the nvCIM macro to perform the secure data-read operation. Finally, the FPGA passed output data from the nvCIM macro to the PC, which compared decrypted data from the nvCIM macro with target plaintext data, the results of which were displayed on an LCD screen.

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Supplementary Figs. 1–6 and Notes 1–4.

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Chiu, YC., Khwa, WS., Yang, CS. et al. A CMOS-integrated spintronic compute-in-memory macro for secure AI edge devices. Nat Electron 6, 534–543 (2023). https://doi.org/10.1038/s41928-023-00994-0

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