Fig. 1: Highly asymmetric channels.
From: Nanofluidic logic with mechano–ionic memristive switches
a, Nanofabrication process flow. Step 0: the starting point is silicon chips (in green) with an SiN membrane (in yellow) of around 20 × 20 microns, a thickness of 20 nm and an aperture with a diameter of approximately 100 nm. Step 1: palladium islands (in grey) are placed by evaporative deposition. As a result of careful tuning of the deposition parameters, palladium islands form, leaving space for ions to flow around them. Step 2: dry transfer emplaces a graphite crystal (in blue) with a lateral dimension of 20–50 µm. b, TEM images. Top, the top view of the SiN aperture after step 1; bottom, a cross-sectional view of a completed HAC device. c, Device and setup. Left, sketch of a finished device, with colours as in a. Black lines indicate typical field lines and fluidic paths. For clarity, the graphite crystal, aperture and islands are not at scale. Right, experimental setup for nanofluidic measurements. d, I–V characteristics (Device A, 50 mHz, 1 M KCl). The I–V curve is composed of loops self-crossing at the origin, the signature of a memristive effect. Arrows indicate the direction of the sweep. The dots show individual data points highlighting the abrupt switching and quasi-discrete conductance states. Inset, G–V curve extracted from d. The conductance is defined as the instantaneous current/voltage ratio, G(t) = I(t)/V(t). Here, the conductance is between 6 and 120 nS, yielding a conductance ratio of 20.
